A Low Voltage All-Digital Phase-Locked Loop Based on Differential Bootstrapped Ring Oscillator
Date Issued
2016
Date
2016
Author(s)
Wei, Chi-Hao
Abstract
Since the first phase-locked loop was proposed in 1930, many applications have been found with phase-locked loops, e.g., the clock generators in digital circuits, local oscillators of communication systems, clock and data recovery circuits, and so on. Phase-locked loops have to achieve accurate phase and frequency synchronization in order to meet the specifications. Therefore, it is very important to design a phase-locked loop which has proper operating frequency range with low phase jitter and low phase noise. Analog phase-locked loops were usually adopted in traditional approach. On the other hand, the digital circuits have many advantages such as low area, low power, and good portability. The research of phase-locked loops are gradually moving toward fully- digitized in recent years except oscillators. It is known as all-digital phase-locked loop. This thesis proposes a 5-stage differential bootstrapped ring oscillator. Its large output swing makes it have good driving capability in low supply voltage. On the other hand, the differential output makes it have low phase noise and much wider applications. This oscillator is then combined with a high-resolution digitally-controlled pMOS array as the digitally-controlled oscillator (DCO) of an all-digital phase-locked loop, and it is fabricated in tsmc 90 nm CMOS technology with frequency divider and other peripheral circuits. The chip area is 950 μm × 850 μm (with pad). When the output frequency is 437 MHz, the phase noise of the digitally-controlled oscillator alone is -96.9 dBc/Hz at 1 MHz offset. The consumption of digitally-controlled oscillator is 225 μW (without buffer), and the total power consumption of the chip is 2.3 mW (with buffer). The chip is verified with the bang-bang phase frequency detector and the digital loop filter which were synthesized on the Terasic DE2-115 Altera FPGA board. When the reference frequency is 6.5 MHz and the output frequency is 416 MHz, the phase noise of the all-digital phase-locked loop is -102.1 dBc/Hz at 1 MHz offset.
Subjects
Phase-Locked Loop
Clock Generator
Local Oscillator
Clock and Data Recovery
Phase Jitter
Phase Noise
All-Digital Phase-Locked Loop
Ring Oscillator
Digitally-Controlled Oscillator
Bang-Bang Phase Frequency Detector
Digital Loop Filter
FPGA
Type
thesis
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