A 40Gb/s low-power analog equalizer in 0.13μm CMOS technology
Journal
2008 Symposium on VLSI Circuits
Pages
216-217
Date Issued
2006-06
Author(s)
Abstract
A 40Gb/s low-power analog equalizer has been realized in 0.13μm CMOS technology. To achieve a peaking gain of 10dB at 20GHz and low power dissipation, an inductive feedback stage is proposed. This inductive feedback stage consumes 3.6mW from a 1.2V supply and the whole equalizer consumes 14.4mW. The chip occupies 0.57×0.44mm 2 . For a 40Gb/s PRBS of 27-1, the measured BER is less than 10–12 and the measured maximum peak-to-peak jitter is 12.6ps.
SDGs
Type
conference paper