A wideband programmable-gain amplifier for 60GHz applications in 65nm CMOS
Journal
International Symposium on VLSI Design, Automation, and Test (VLSI-DAT)
Date Issued
2013-06
Author(s)
Abstract
In this paper, a novel circuit topology of programmable-gain amplifier (PGA) is presented for 60GHz applications. To attain wideband characteristics, a modified Cherry-Hooper amplifier is employed as the gain cell while series binary-weighted resistor networks are adopted in both the feedback path and the source degeneration. As a result, a pseudo-exponential approximation is performed, leading to programmable linear-in-dB gain-tuning operations. By cascading four gain cells along with a dc offset cancellation circuit and an output buffer stage, a 3-bit digital-controlled wideband PGA is implemented. Fabricated in a 65nm CMOS process, the proposed PGA exhibits a 3dB bandwidth more than 1.92 GHz and a dB-linear gain range from -9.6 to 34.5 dB with a maximum gain error of ±0.54 LSB. The core circuit consumes a dc power of 4.9 mW from a 1-V supply voltage while the chip occupies a small active area of 0.03 mm 2 .
SDGs
Type
conference paper