Algorithm and VLSI Architecture Design of Multimedia Content Analysis System
Date Issued
2010
Date
2010
Author(s)
Chen, Tse-Wei
Abstract
Nowadays, thanks to the development of semiconductor technology, there are more and more versatile applications in Consumer Electronics (CE) products. Different kinds of CE products, such as cellular phones, digital still cameras, portable computers, are gradually integrated into one single system. In the near future, a CE product might include different functionalities, including making phone calls, sending e-mail, and taking/storing photos. At the same time, the advance of memory is also astonishing. The size of flash memory is increasing, but its price is decreasing steadily. Obviously, the new memory technology might replace the traditional hard disk for data storage. Because of the development of the Internet and the large storage of data, managing multimedia content becomes an important and indispensable task. Therefore, the integration with different kinds of functionalities and the increase of multimedia data result in the necessity of automatic multimedia content analysis for CE products. In embedded systems for CE products, the traditional CPU/RISC and ASIC cannot satisfy both the flexibility and performance requirements of multimedia applications based on their architectures, so the exploration of new design methodologies and solutions are needed for next-generation applications.
In this dissertation, new implementation methods and frameworks of multimedia content analysis are proposed. From algorithm designs, architectural analyses, hardware architectural designs, software/hardware co-designs, and SoC designs, a systematic approach is adopted. The proposed methods provide a series of new solutions to next-generation applications for consumer electronics (e.g. mobile devices). To effectively analyze the contents of multimedia, feature extraction and machine learning algorithms are both indispensable. There are lots of machine learning algorithms that are widely employed in different applications, and they can be regarded as essential components or building blocks for multimedia content analysis. To handle the supervised learning and unsupervised learning algorithms in machine learning, both high-performance hardware architectures and reconfigurable hardware architectures are proposed. For high-performance architectures, K-Means clustering algorithm is the focus in this dissertation because of its popularity and importance, and its applications are also demonstrated. A total of four kinds of K-Means architectures are developed. For reconfigurable hardware architectures, two System-on-a-Chip (SoC) architectures with different features are proposed. These systems can process a large amount of data in parallel and perform feature extraction with high bandwidth, and they can also deal with various kinds of machine learning algorithms, such as K-Means clustering, K-Nearest Neighbor classification, Gaussian Mixture Model-based classification, Support Vector Machine, and Artificial Neural Network.
In short, the contribution of this dissertation consists essentially of two algorithms for video and image segmentation, one software/hardware co-design platform, four different kinds of architectures for K-Means clustering, and two SoCs for multimedia content analysis. The content of this dissertation can also be regarded as a series of new solutions to multimedia content analysis for CE products.
Subjects
digital circuit
multimedia content analysis
hardware architecture
machine learning
Type
thesis
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