Improving Metal-Semiconductor Contact Conductance with Patterned Interface of Square-Hole Array
Date Issued
2012
Date
2012
Author(s)
Li, Jong-Lih
Abstract
A well-patterned metal-semiconductor interface with square-hole array on a semiconductor substrate, fabricated by electron-beam lithography, is used to improve metal-semiconductor-contact conductance (MSCC) by tuning Schottky barrier through designing arrayed nano-scale interfaces. The MSCC increases with decreased hole size from 800, 400, to 200nm. Then, the well-known Al/Si system is applied as the vehicle to verify the newly developed methodology. It is also expected that the contact problems in P-type GaN can be improved.
Instead of conventional heavy-doping or annealing process, the developed methodology can be used to improve the MSCC from 0.004 to 13.390 µS in compared to the sample without holes. The cross-section TEM results show that the hole arrays are fully covered by the deposited Al film. The Al nanocrystals, with in-plane grain sizes around 100nm, appear inside and near the holes. The increase of Al crystallization (AC) further shows the functionality of the smaller holes. In hole-pitch dependence experiment, the hole-array areas are also verified as the active areas of the conductance. Therefore, the nano-crystalline Al/Si interfaces are the areas contributing to the larger conductance. In addition, the interfacial oxygen content (PC) decreasing with hole sizes can be explained by the AC increment. Both results agree very well with the size dependence of the MSCC. Hence, an experimental model, expressed as that MSCC is proportional to AC divided by the square of PC, is also established. Compared with other methodologies, the present methodology has the advantages of the higher flexibility of designing, uniformity of manufacturing and compatibility with the semiconductor processing. Moreover, the result verifies that the MSCC can be improved and designed through the developed methodology.
For further improving MSCC, the hole-array sample is also annealed and optimized. The best MSCC is about 76.46 µS/cm2, which is around 9200 times better than that of annealed sample without holes. And the annealing temperature of 340℃ is 110℃ lower than that of the conventional processing. To ascribe the effect with a different scenario, currently, a Raman scattering investigation is also conducted. The Al/Si interfacial stress, found in the annealed samples, is also calculated. The result can explain an obviously Si-rich interface, and which can influence Schottky barrier, with a lower PC in the best annealed hole-array sample.
Moreover, the functionality of hole array has been successfully identified. The results based on engineering the metal-semiconductor interface promises the possibility to be an alternative other than conventional ones to achieve ohmic contacts, especially for the nanodevices that can not be heavily doped and fabricated through high-temperature processing. Most significantly, a more robust and well-controlled interface can be obtained and expected to overcome the obstacles in the newly introduced materials systems and the devices with their size reduced to the deep nano-scale domain. Meanwhile, the inherently non-planar Al/Si interface can be prevented.
Subjects
metal-semiconductor-contact conductance
electron-beam lithography
crystallization
nano-crystals
Raman scattering
Schottky barrier
non-planar interface
Type
thesis
File(s)![Thumbnail Image]()
Loading...
Name
ntu-101-D91943020-1.pdf
Size
23.32 KB
Format
Adobe PDF
Checksum
(MD5):f289a56ad46ed7893a75e2245f08c08a