An Asynchronous Design for Testability and Implementation in Thin-film Transistor Technology
Journal
Journal of Electronic Testing
Journal Volume
27
Journal Issue
2
Pages
193-201
Date Issued
2011-01
Author(s)
Abstract
This paper presents a scan chain design for dual-rail asynchronous circuits. This is a true asynchronous scan chain because no clock is needed even in scan mode. This is a full-scan design for testability (DfT) so only combinational automatic test pattern generation (ATPG) is needed and the fault coverage of generated test patterns is very high. This technique can be applied to various kinds of asynchronous circuits, including pipelines, state machines, and interconnects. Experiments on an 8051 datapath circuit show that the coverage is as high as 99.59%. This technique has been proven to work successfully in 8 μm Thin-film transistor (TFT) technology on the glass. © 2011 Springer Science+Business Media, LLC.
Type
journal article