Binary Turbo Coding with Interblock Memory
Journal
IEEE Wireless Communications and Network Conference (WCNC 2007)
Pages
77-82
Date Issued
2007-03
Author(s)
Abstract
We investigate the performance of binary codes T constructed from turbo coding with interblock memory. The encoding of T is implemented by serially concatenating a multiplexer, a multilevel delay processor, and a signal mapper to the encoder of a conventional binary turbo code C. With such a construction, in T, there is some irregularity for the code bits in C. To provide more variety of irregularity, we can construct T C which is obtained by passing only a fraction of C through a multilevel delay processor and a signal mapper. We propose iterative decoding between adjacent codewords (IDAC), which provides error performance much better than the iterative decoding within a single codeword (IDSC). Simulation shows that T can have a lower error floor than C for either short or long code length. In some cases, T C can provide better error floors and waterfall regions than C.
Type
conference paper