A 6-b 1.3Gs/s A/D Converter with C-2C Switch–Capacitor Technique
Journal
IEEE VLSI-DAT
Pages
109-112
Date Issued
2006-04
Author(s)
Y-M Liao
Abstract
A 6-b 1.3-Gs/s pipelined successive-approximation analog-to-digital converter (ADC) is presented. Employing improved-MMS and C-2C architecture, the circuit operates in high speed and low power consumption. With open-loop architecture, the T/H circuit can work at a high conversion rate. The proposed architecture reduces the static power consumption by charge redistribution digital-to-analog converter (DAC) and lowers the accuracy requirement of the capacitor in the conventional successive-approximation (SA)-ADC by the C-2C architecture. Designed in a 0.18-mum technology, the ADC operates at 1.3-Gs/s clock rate while power dissipation is 196 mW. The FFT simulation result shows that the SNDR is 34 dB at 130-MHz input frequency and 1.3-Gs/s conversion rate
SDGs
Type
conference paper