Jump Scan: A DFT Technique for Low Power Testing
Date Issued
2005
Date
2005
Author(s)
Chiu, Min-Hao
DOI
en-US
Abstract
This paper presents a Jump scan technique (or J-scan) for low power testing. The J-scan shifts two bits of scan data per clock cycle so the scan frequency is halved without increasing the test time. The experimental data show that the proposed technique effectively reduces the test power by 67% compared to the traditional MUX scan. The presented technique requires very few changes in the existing MUX-scan design for testability (DFT) methodology and needs no extra computation. The penalties are area overhead and speed degradation.
Subjects
低功率測試
可測試設計
自我測試
Low Power Testing
Scan
DFT
Delay Fault Testing
BIST
Type
thesis