Fast fab scheduling rule selection by ordinal comparison-based simulation
Journal
1999 IEEE International Symposium on Semiconductor Manufacturing, ISSM 1999 - Conference Proceedings
Pages
53-56
Date Issued
1999-10
Date
1999-10
Author(s)
Abstract
In this paper, an ordinal comparison (OC)-based simulation tool is designed and applied to achieve fast selection of wafer release and lot dispatching rule combination for fab operations. By comparing relative orders of performance among scheduling rules to a specified level of confidence, the OC approach reduces simulation time significantly. The tool consists of (1) a discrete event simulator, (2) a fab model database, (3) a library of scheduling rules, (4) a library of performance indices, (5) an ordinal comparator, and (6) a computation budget allocation. Rule selections from a set of prominent fab scheduling rules under frequently considered fab performance indices such as mean and variance of cycle time and smoothness are studied over various time horizons by using a benchmark fab model. Results demonstrate a potential improvement in efficiency over traditional simulation by two orders of magnitude. In addition to insights about static selection of rules over various objectives and time horizons, our simulation studies also indicate the necessity of dynamic selection. © 1999 IEEE.
Other Subjects
Benchmarking; Budget control; Discrete event simulation; Manufacture; Optimal systems; Scheduling; Benchmarking; Computer simulation; Database systems; Industrial economics; Industrial electronics; Mathematical models; Production control; Resource allocation; Scheduling; Silicon wafers; Budget allocation; Discrete-event simulators; Dynamic selection; Fab performance; Orders of magnitude; Performance indices; Scheduling rules; Simulation studies; Semiconductor device manufacture; Semiconductor device manufacture; Computation budget allocation; Discrete event simulators; Fabrication model databases; Ordinal comparison (OC)-based simulation
Type
journal article
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