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  4. A Comprehensive Study of Bias Temperature Instability, Strain, and Memory Effects on Polycrystalline Si Thin-Film Transistors
 
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A Comprehensive Study of Bias Temperature Instability, Strain, and Memory Effects on Polycrystalline Si Thin-Film Transistors

Date Issued
2009
Date
2009
Author(s)
Huang, Ching-Fang
URI
http://ntur.lib.ntu.edu.tw//handle/246246/189146
Abstract
  In this dissertation, bias temperature instability, strain and memory effects have been comprehensively studied on polycrystalline silicon (poly-Si) thin-film transistors (TFTs). In Chapter 2 and Chapter 3, static NBTI and PBTI are investigated on p-channel and n-channel poly-Si TFTs. For PBTI of p-channel poly-Si TFTs and NBTI of n-channel poly-Si TFTs, a subthreshold hump is induced after sufficient stress. The hump is attributed to the edge transistor along channel width direction, and is independent of nominal channel width. Carriers are injected into insulator via Fowler-Nordheim (F-N) tunneling, leading to the threshold voltage shifts. Higher electric field at edges yields more trapped electrons to create the hump.  For NBTI of p-channel poly-Si TFTs, the negative threshold voltage is mainly attributed to the generation of donor type interface traps. The electrochemical reaction is driven by vertical electric field, and is facilitated at elevated temperature. For PBTI of n-channel poly-Si TFTs, positive VT shift is attributed to electron trapping in gate insulator. For VG smaller than 20 V, F-N tunneling is dominant and VT shift increases with stress time. For VG larger than 25 V, Frenkel-Poole emission is dominant and VT shift decreases with stress time. Since poly-Si TFTs in the driver circuits are subjected to high frequency voltage pulses in the practical applications. Therefore, it is of great importance to investigate the dynamic bias instability of both n-channel and p-channel poly-Si TFTs. Impact ionization is induced by lateral electric field when VG switches from inversion or depletion to accumulation bias due to the slow formation of accumulation region. For n-channel poly-Si TFTs, since grain boundary barrier height increases, drain current degrades significantly after stress. For p-channel poly-Si TFTs, drain current increases with time, then, decreases with time for long-term stress. The initial current increase is attributed to decrease of effective channel length. As stress time increases, the grain boundary barrier height increases to degrade the drain current. Noticeably, short channel devices suffer more degradation, implying a tradeoff between performance and reliability. Strained-Si technology has been extensively used in CMOS industry to enhance carrier mobility. However, the strain effect of poly-Si has not been reported yet. In this dissertation, external mechanical tensile strain is applied to n-channel poly-Si TFTs to investigate the drain current variation. Drive current enhances +5.7% but degrades -4.4% for longitudinal strain and transverse strain, respectively. The poly-Si film is mainly composed of (111)-oriented grains, measured by transmission electron diffraction pattern and powder x-ray diffraction. In addition, no obvious current change is observed for biaxial tensile strain due to the 6-fold symmetry of electron valleys of (111)-oriented Si.  Improvement of poly-Si TFT performance is essential in order to achieve value-added displays where various functional circuits are integrated on the substrate. The integration level is proceeding from simple digital circuits to digital circuits such as digital-analog converters (DACs) and DC-DC converters. For the future system-on-panel (SOP) integrations, CPU, memory, and controller are combined into a single high-quality display. In the last part of the dissertation, a long data retention memory is realized by filling/emptying grain boundary traps of n-channel poly-Si TFTs. The fabrication process of the memory cell does not require additional processes, which is highly promising for future system-on-panel applications.
Subjects
poly-Si TFTs
bias temperature instability (BTI)
strained-Si technology
nonvolatile memory
Type
thesis
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