Designs and Implementations of Receiver Analog Front-end Circuits for 10-Gb/s Optical Communication Systems
Date Issued
2006
Date
2006
Author(s)
Huang, Huei-Yan
DOI
en-US
Abstract
As a result of the enormous growth of internet and intranet, the rapid increase of data traffic leads to a vast demand of huge capacity of optical communication systems. In recently published papers, optical transmission systems operating at 10 Gb/s have been developed to fulfill such demand. Data rates in optical communication systems are mainly limited by their electrical interfaces with the available optoelectronic devices such as the lasers in transmission end and the photo-diode in the front-end of the receiver. Therefore, the most speed critical integrated circuits (ICs) in the systems are the analog front-end including transimpedance amplifier and limiting amplifier in the receiver and the laser driver in the transmitter.
The 10-Gb/s transimpedance amplifier (TIA) presented in this thesis is implemented in a standard 0.18-μm CMOS technology. In order to improve the overload characteristic, the automatic gain control (AGC) composed of the average detector, the comparator and the voltage-current converter followed by the off-chip loop filter is included in this work. The detail analysis of the AGC behavior model including linear and bang-bang operation is presented to predict the performance of the gain control mechanism. The experimental results show the TIA achieves a transimpedance gain of 45 dBΩ and a -3-dB bandwidth over 8.6 GHz with 60-mW power dissipation from a 2.0-V supply. Along with the AGC circuit, the fabricated circuit that is tested in 10-Gb/s, 231-1 PRBS exhibits a sensitivity of -21 dBm and an overload threshold of 1 dBm.
An inductorless circuit technique is presented for CMOS limiting amplifiers. By employing the third-order interleaving active feedback, the bandwidth of the proposed circuit can be effectively enhanced while maintaining a suppressed gain peaking within the frequency band. Using a standard 0.18-um CMOS process, the limiting amplifier is implemented for 10-Gb/s broadband applications. Consuming a dc power of 189 mW from a 1.8-V supply voltage, the fabricated circuit exhibits a voltage gain of 42 dB and a -3-dB bandwidth of 9 GHz. With a 231-1 pseudo-random bit sequence at 10 Gb/s, the measured output swing and input sensitivity for a bit-error-rate of 10-12 are 300 and 10 mVpp, respectively. Due to the absence of the spiral inductors, the chip size of the limiting amplifier including the pads is 0.68x0.8 mm2 where the active circuit area only occupies 0.32x0.6 mm2.
Subjects
百億位元光纖通訊
接收機
前端電路
10-Gb/s Optical Communication Systems
Receiver
Analog Front-end Circuits
Type
thesis
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