40Gb/s high-gain distributed amplifiers with cascaded gain stages in 0.18μm CMOS
Journal
IEEE International Solid-State Circuits Conference (ISSCC 2007)
Pages
538-539
Date Issued
2007-02
Author(s)
Abstract
High-gain distributed amplifiers (DA) using cascaded stages as distributed cells are implemented in 0.18μm CMOS technology. Two DAs with 3times3 and 2times4 configurations are demonstrated for 40Gb/s applications. While consuming 250mW from a 2.8V supply, a GBW of up to 394GHz is achieved.
SDGs
Type
conference paper