Enhanced Electrical Performance of Van der Waals Heterostructure
Journal
Advanced Materials Interfaces
Journal Volume
8
Journal Issue
6
Date Issued
2021
Author(s)
Abstract
In this study, a novel van der Waals (vdW) heterostructure field-effect transistor (FET) using vdW stacking as next-generation device architecture is demonstrated. The MoS2/WS2 heterostructure FET exhibits a large improvement in the drain current and field-effect mobility (from 43.3 to 62.4 cm2 V?1 s?1) compared with single MoS2 FET. Such significant enhancement is mainly due to the charge-transfer effect. The vdW self-encapsulation effect in the device channel also helps to reduce the Schottky barrier height from 120 to 52 meV at the contact interface. Finally, the WS2/MoS2/WS2 double heterostructure FETs further boosts the mobility up to 102.5 cm2 V?1 s?1 at room temperature (25?°C) and 169.7 cm2 V?1 s?1 at 30 K. The much higher mobility exhibited at the lower temperature indicates the suppression of Coulomb scattering. Thus the electrical performance of the double-heterostructure FETs can be further enhanced. ? 2021 Wiley-VCH GmbH
Subjects
Charge transfer; Drain current; Layered semiconductors; Molybdenum compounds; Schottky barrier diodes; Tungsten compounds; Van der Waals forces; Coulomb scattering; Device architectures; Double heterostructures; Electrical performance; Field-effect mobilities; Heterostructure field effect transistors; Lower temperatures; Schottky barrier heights; Field effect transistors
SDGs
Type
journal article