Ion Implant Isolation for Quantum Tunneling Devices
Date Issued
2015
Date
2015
Author(s)
Lung, De-Hau
Abstract
For conventional metal-oxide-semiconductor field-effect transistors, thermionic injection sets a limit to the subthreshold swing (> 60 mV/decade), leading to an increase of power consumption at off-state with the device scaling. Based on the modulation of the band-to-band tunneling probability by gate, a tunnel field-effect transistor (TFET) could overcome the thermionic limit and thus, provide a lower supply voltage and achieve lower power consumption. To investigate the tunneling probability, tunnel diodes are used because of its reduced complexity compared to TFETs. To estimate the tunnel current density, the diode size needs to be scaled down to sub-micrometer or even a smaller dimension. The mesa structure is not suitable for electrical probing, so we propose a full planarization process for the fabrication of tunnel diodes by ion implant isolation technology to compare with normal mesa structure and other planarized devices by BCB. The ion implant isolation process has been widely used in III-V semiconductor, but not yet for group IV semiconductors. To investigate the resistivity in silicon or germanium by ion implant, we investigate the effects of implant parameters and annealing temperature on the resistivity. The experiment results show that the thermal (budget) stability for silicon and germanium can be up to 550℃ and 350℃, respectively. We proposed a novel vertical TFET structure and its required process steps. By aligning the tunneling direction with the gate electric field and the insertion of the spacer layer between the source and the drain regions, the leakage current can be effectively suppressed. TCAD simulation was performed to study the effects of various structural parameters on vertical TFETs. The best Ion/Ioff is 107 (at Voverdrive =0.8 V), the minimal subthreshold swing (SSmin) is 6 mV/decade, and SS of less than 60 mV/decade was also obtained within five orders of magnitude of current. Last, we fabricated the SiGe TFET devices. The experimental data shows a poor Ion/Ioff of ~ 102. The preliminary analysis suggests the quality of the etched sidewall would affect the oxide capacitance, leading to poor electrostatic gate control. By improving the oxide/sidewall interfacial quality and optimizing the device structure, we expect to achieve a vertical TFET with much better performance.
Subjects
TFET
Ion Implant Isolation
planarization process
Type
thesis
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