A Wide-Range Delay-Locked Loop with a Fixed Latency of One Clock Cycle
Date Issued
2002-08
Date
2002-08
Author(s)
張湘輝
DOI
20060927122802710152
Abstract
With the evolution and continuing scaling of CMOS technologies, the demand of high speed and
high integration density VLSI systems have exponential growth recently. However, the synchronization
problem among IC modules is undoubtedly important and becoming one of the bottlenecks for high
performance systems.
Publisher
臺北市:國立臺灣大學電機工程學系
Type
thesis
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Format
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Checksum
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