硬體描述語言低功率架構設計(3/3)

The goal of this project is to design a synthesis flow for the low power circuit at
behavioral level. As the technology scales down to the nanometer dimensions, the
static power consumption has become as important as dynamic power consumption.
To manage the power consumption, in this project, we propose a low power
method, which considers the dual supply voltage (Vdd) and the dual threshold
voltage (Vth) at the same time, to deal with the scheduling problem in the
behavioral synthesis stage. A flexible design space of power can be achieved when
we use the proposed method. A combined algorithm of GA (Genetic Algorithm)
and SA (Simulated Annealing) is used to solve the scheduling problem.
Experimental results illustrate 41.6% power reduction on average.