ECO Timing Optimization Using Spare Cells and Technology Remapping
Date Issued
2006
Date
2006
Author(s)
Chen, Yen-Pin
DOI
en-US
Abstract
Spare cells rewiring is a technique used to fix defects or
deficiencies after the placement stage. It is traditionally done by manual work but becomes extremely hard nowadays. In this thesis, we propose the first spare cells selection algorithm consisting of two
phases to optimize timing of the circuit by rewiring spare cells. In the first phase, we apply gate sizing and buffer insertion to all timing violated paths to fix timing violations. In the second phase, we further fix timing violations by extracting timing critical parts
and apply technology remapping to them. Experimental results based on five industrial benchmarks show that our algorithm can fix up to 99.82\% of the total negative slack, and the runtime is very short.
The experimental results show that our algorithm is efficient and effective.
Subjects
預留元件
技術映射
spare cell
technology mapping
buffer insertion
Type
thesis
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