Power and Timing Optimization for Hybrid SoC Designs with Asynchronous/Synchronous Designs
Date Issued
2013
Date
2013
Author(s)
Ho, Kuan-Hsien
Abstract
A system on a chip (SoC) is an integrated circuit (IC) that integrates multiple functional blocks in a chip for a specific application. For high-performance applications, more and more SoC designs combine functional blocks of asynchronous and synchronous circuits into the same chip, where asynchronous circuits are expected to achieve higher performance than their synchronous counterparts. On the other hand, the decreasing feature sizes enable IC designers to integrate more functional blocks into a chip than ever before. As the scale of integration grows, the increasing power density, however, forces the designers to make a trade-off between the functionality and power consumption of their chips. Reducing power consumption thus becomes a crucial concern for modern SoC designs.
This dissertation presents two strategies to minimize the power consumption of asynchronous and synchronous circuits. For asynchronous circuits, template-based design flow is widely used to automate the design of modern asynchronous circuits, where template structures strongly correlate to the power consumption and performance of the resulting circuits. Consequently, this dissertation proposes an asynchronous template that can effectively reduce glitch power consumption of asynchronous pipelines. For synchronous circuits, gate sizing and threshold voltage (Vth) assignments are two key techniques in industrial low-power design flow. Gate sizing and Vth assignments can be applied throughout the entire RTL-to-GDS flow for power and timing optimization of chip designs. This dissertation presents a systematic framework using gate sizing and Vth assignments for leakage power reduction. To be efficient, this dissertation also presents an optimality-preserving problem-size reduction technique and two parallelization methods for the proposed framework.
Although the above two strategies are effective to power reduction, modern IC designs often undergo multiple engineering change orders (ECOs) in late design stages to repair design or specification errors. The resulting designs may not be able to meet their timing requirements. Consequently, this dissertation further presents two metal-only ECO techniques for timing optimization using spare cells. One is derived from technology mapping to restructure timing critical sub-circuits iteratively, and the other is derived from clock scheduling to utilize clock skew for timing optimization. Experimental results show the effectiveness and efficiency of all the proposed approaches. Finally, this dissertation provides some directions for future research.
Subjects
系統單晶片
非同步電路設計
元件尺寸最佳化
臨界電壓分配
工程修改命令
Type
thesis
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