A high-resolution and fast-conversion time-to-digital converter
Resource
Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on
Journal
IEEE International Symposium on Circuits and Systems
Journal Volume
1
Date Issued
2003-05
Date
2003-05
Author(s)
DOI
N/A
Abstract
This paper describes a design of time-to-digital converter (TDC), which has the features of high-resolution and fast conversion. With the aid of the gate delay difference technique, the TDC can achieve a sub-gate delay resolution. The flash-type operation enables the TDC to resolve the time difference for fine conversion in less than one reference clock cycle. The differential non-linearity (DNL) can be less than /spl plusmn/0.03 LSB and integral non-linearity (INL) less than /spl plusmn/0.04 LSB. We confirm the results based on 0.35 /spl mu/m CMOS process technology.
SDGs
Type
conference paper
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