A 12Gb/s AC coupled chip-to-chip transceiver
Date Issued
2009
Date
2009
Author(s)
Wu, Yi-Chi
Abstract
Transceiver is the critical circuit in many systems. With the growing of the media technology, high speed I/O is indispensable for many applications. Moreover, for the portable applications, low power consumption is also an important issue. Thus how to design a high speed and low power I/O is the main propose of this thesis.his thesis describes a low-power and high-speed AC coupled transceiver architecture for high density interconnects. This transmitter can convert non-return to zero (NRZ) data into return to zero (RZ) pulse, then sending pulse through transmission line, and recovering pulse to NRZ data at receiver. At the transmitter side, we use phase-locked loop with complementary transmission line to be clock signals. At the receiver side, sense amplifier is used to recover NRZ data from pulse. sing this low swing pulse transceiver, 12Gb/s chip-to-chip communication is demonstrated through a wire-bonded AC coupled interconnect (ACCI) channel with 75-fF coupling capacitors, across 10-cm FR4 micro-strip lines. A test chip was fabricated in TSMC 0.18-um CMOS technology, and for 2^15-1 PRBS at 12Gb/s, transmitter and receiver circuits consumed 21.3mW and 13.5mW respectively with a bit error rate less than 10^-12 . It occupies an active area of 500x735um2 and 250x350um2.
Subjects
AC coupled interconnect (ACCI)
PLL
transceiver
low swing pulse
Type
thesis
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ntu-98-R96943124-1.pdf
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