A broadband doubler with harmonic rejection in 90nm CMOS
Journal
2015 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2015 - Proceedings
Pages
25-27
Date Issued
2016
Author(s)
Abstract
In this paper, we present a broadband frequency doubler with harmonic rejection using 90nm CMOS process. The balanced frequency doubler adopts cascode topology with class C bias to maximize second order harmonic generation. An elliptic low pass filter is integrated inside the cascode structure to suppress the fourth and higher order harmonic power. The 3-dB bandwidth of this frequency doubler is from 42 to 90 GHz with 8 to 11 dB conversion loss under 5-dBm input drive.
SDGs
Type
conference paper