Algorithms and Architectures of Thermal-Aware Three-Dimensional Network-on-Chip Systems
Date Issued
2012
Date
2012
Author(s)
Chao, Chih-Hao
Abstract
As the advance of semiconductor technology, the integration complexities become higher. For high performance chip multi-processor systems, Network-on-Chip (NoC) has become a common infrastructure for data exchange. By combining with the three-dimensional (3D) IC technology, 3D NoC has the advantages of smaller form factor, leading to lower transmission latency. Besides, due to the extra directions for connection, the router has higher bandwidth. These advantages make 3D NoC capable of achieving higher performance. However, due to the characteristic of high switching activity, NoC has comparable thermal impact as processors, and routers is one of the sources generating thermal hotspots. Due to the longer heat conduction path, larger cross-sectional power density, and varying cooling efficiency of different layers, the thermal problem of 3D NoC is severer than 2D NoC. Therefore, the performance gain of 3D integration will be limited by the peak temperature and the thermal limit.
In this dissertation, we aim at maximizing the throughput of the network by proposing new algorithm and architecture. The design constraint is that the peak temperature of the NoC should be under the thermal limit. In the first part of this dissertation, a traffic-thermal mutual-coupling co-simulation environment is proposed and validated. The proposed simulator enables the design of thermal-aware 3D NoC systems.
In the second part of this dissertation, we propose a new routing-based traffic migration and buffer allocation design scheme for 3D NoC systems without embedded thermal sensors. Due to the varying cooling efficiency of the different layers, the traditional load-balancing design scheme and the traditional temperature-balancing design scheme for 2D NoC cannot achieve the maximal throughput. By redistributing the traffic loading and the buffer depth among each layer, the maximal throughput in steady state can be improved by 13.5% without upgrading heat dissipater.
For 3D NoC with embedded thermal sensors, the traditional global-throttling-based run-time thermal management (RTM) scheme of 2D NoC results in huge degradation in network availability. Similarly, the traditional distributed-throttling-based RTM scheme suffers from the long cooling time. Therefore, we propose a new RTM scheme and a temperature-traffic control framework. The collaborative vertical-throttling-based RTM scheme actively creates the null region of heat generation for fast heat dissipation. Comparing to traditional RTM schemes, the performance impact of RTM is reduced to one-twelfth.
Because traditional routing algorithms cannot handle the time-varying network topology resulting from RTM, the congestion-tree occupies the network, leading to poor throughput. Hence, in the fourth part of this dissertation, we propose the transport layer assisted routing scheme and the corresponding algorithms and architectures. With this scheme, all fail delivery cases are removed. Therefore, the 3D NoC can sustain its working status in high performance.
In summary, the proposed schemes can mitigate the design challenge of 3D NoC systems. Under the same cooling device and environment, the 3D NoC system can be kept thermal-safe. Besides, the advantage of 3D integration, performance improvement, is preserved because the thermal-limited performance back-off is reduced.
Subjects
Three-dimensional Network-on-Chip
Thermal management
Thermal-aware algorithm and architecture
Type
thesis
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