Performance Modeling for Multicore Embedded Processors based on Verilog-to-SystemC Conversion
Date Issued
2009
Date
2009
Author(s)
Liaw, Yuh-Hung
Abstract
With the life-cycle of consumer electronics getting short in recent years, to shorten development time, hardware/software co-design has become an important issue. Traditionally, hardware description languages, e.g. Verilog and VHDL, are commonly used to describe and model the hardware. Unfortunately, the usage of language is hard to be integrated with the development of software. SystemC solves this problem by describing the hardware with C++ language and C++ language library functions. owever, converting an existing Verilog design can be very challenging. Existing tools failed to produce correct translation for sophisticated Verilog code, such as OpenSPARC T1. They cannot support certain Verilog constructs because it is hard to translate these constructs directly into SystemC to maintain correct semantics. Thus, we designed an innovative Verilog-to-SystemC translation tool, called V2X, with techniques developed to overcome those problems. We took a two-stage approach to make the translation flexible and extendible. In this thesis, we describe how performance modeling can be done for multicore embedded processors based on Verilog-to-SystemC conversion, with OpenSPARC T1 as a case study. Using V2X, we successfully translated OpenSPARC T1 design into SystemC, and we show that the SystemC version improved the simulation speed by ~40 times.
Subjects
Computer Language Translation
Type
thesis
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