Optimization of Clock Gating Circuits with Timing Considerations
Date Issued
2011
Date
2011
Author(s)
Chuang, Shun-Hsiang
Abstract
Power consumption is an essential concern in modern circuit designs. Clock gating, an efficient technique for power reduction, has been widely used. The basic structure of a circuit using clock gating could generally be classified into three major parts: the clock-gating function, the next state function, and the clock-gating circuits. In recent years, researchers have mainly focused on simplifications of the next-state function and the clock-gating function. In contrast, the optimization of the clock-gating circuit has seldom been addressed. To the best of our knowledge, we introduce the first work in the literature that addresses on the optimization of the clock-gating circuit with timing consideration. We propose an efficient V-shaped framework which consists of a series of top-down splittings and bottom-up mergings. Experimental results reveal the effectiveness and the robustness of the proposed approach. Compared to the three top-performance teams in the 2011 CAD Contest, we achieve an 14.6% lower cost in average. Also, while the three teams fail to generate an solution when the timing constraint is hard to satisfy, we succeed in contrast.
Subjects
clock gating
timing consideration
power
clock network
Type
thesis
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