A 0.13μm hardware-efficient probabilistic-based noise-tolerant circuit design and implementation with 24.5dB noise-immunity improvement
Journal
2007 IEEE Asian Solid-State Circuits Conference
Pages
316-319
Date Issued
2007
Author(s)
Abstract
As the size of CMOS devices is scaled down to the nanoscale level, noise interferences start to significantly affect the VLSI circuit performance. Because the noise is random and dynamic in nature, a probabilistic-based approach is more suitable to handle signal errors than the conventional deterministic circuit designs. However, probabilistic-based designs cost larger hardware area. In this paper, we design and implement a hardware-efficient probabilistic-based noise-tolerant circuit, an 8-bit Markov Random Field carry lookahead adder (MRF_CLA), in 0.13μm CMOS process technology. The measurement results show that the proposed MRF_CLA can provide 24.5dB of noise-immunity enhancement as compared with its conventional CMOS design. Moreover, the transistor count can be saved 42% as compared to the state-of-art MRF design [1].
SDGs
Type
conference paper