An automatic router for the pin grid array package
Resource
Design Automation Conference, 1999. Proceedings of the ASP-DAC '99. Asia and South Pacific
Journal
Asia and South Pacific Design Automation Conference, 1999. ASP-DAC '99
Pages
-
Date Issued
1999-01
Date
1999-01
Author(s)
DOI
N/A
Abstract
A Pin-Grid-Array (PGA) package router is presented in this paper. Given a chip cavity with a number of I/O pads around its boundary and an equivalent number of pins distributed on the substrate, the objective of the router is to complete the planar interconnection of pad-to-pin nets on one or more layers. This router consists of three phases: layer assignment topological routing, and geometrical routing. Examples tested on a windows-based environment show that our router is efficient and can complete the routing task with less substrate layers. Compared to manual routing, this router features a friendly graphic user interface and can be practically applied to VLSI packaging.
Type
journal article