Skip to main content
English
中文
Log In
Log in
Log in with ORCID
NTU Single Sign On
Have you forgotten your password?
Home
College of Electrical Engineering and Computer Science / 電機資訊學院
Electrical Engineering / 電機工程學系
MTCMOS low-power optimization technique (LPOT) for 1V pipelined RISC CPU circuit
Details
MTCMOS low-power optimization technique (LPOT) for 1V pipelined RISC CPU circuit
Journal
ICECS
Pages
60-63
Date Issued
2014-12
Author(s)
C. B. Hsu
Y. S. Hong
J. B. Kuo
JAMES-B KUO
DOI
10.1109/icecs.2014.7049921
URI
http://scholars.lib.ntu.edu.tw/handle/123456789/388606
Type
conference paper
