A 6-bit 500-Ms/s digital self-calibrated pipelined analog-to-digital converter
Resource
Advanced System Integrated Circuits 2004. Proceedings of 2004 IEEE Asia-Pacific Conference on
Journal
Advanced System Integrated Circuits 2004
Pages
Proceeding-s
Date Issued
2004-08
Date
2004-08
Author(s)
Chen, Yu-Hsun
DOI
N/A
Abstract
A 6-bit 500-Ms/s digital self-calibrated pipelined A/D converter is presented. Employing open-loop amplifiers in one bit conversion per stage architecture, the circuit operates in high speed and low power consumption. Using constant-g/sub m/ biasing technique, the open loop amplifier is process-and-temperature insensitive. Comparator offset and full-scale error are removed by digital self-calibrated correction mechanism. Designed by a 0.18-/spl mu/m technology, the A/D converter operates at 500-MHz clock rate while dissipating 47 mW. The FFT simulation result shows that the SNDR is 33.52 dB at 51-MHz input frequency and 500-MSPS conversion rate.
SDGs
Type
journal article
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