Approximate Adder Tree Design with Sparsity-Aware Encoding and In-Memory Swapping for SRAM-based Digital Compute-In-Memory Macros
Part Of
2024 IEEE 6th International Conference on AI Circuits and Systems, AICAS 2024 - Proceedings
Start Page
362
End Page
366
ISBN (of the container)
979-835038363-8
Date Issued
2024-04-22
Author(s)
Abstract
SRAM-based digital compute-in-memory (DCIM) is a promising solution to accelerate the extensive multiply-and-accumulate (MAC) operations in deep neural networks (DNNs). Despite its remarkable potential to enhance performance and efficiency, the adder tree circuits dominate the power and area. While directly replacing the exact adder tree with approximate circuits can greatly reduce the overheads, it also induces severe accuracy drop without a laborious retraining process. This work adopts an OR-based approximate adder tree as a baseline and proposes two techniques to recover the accuracy drop without retraining the model: sparsity-aware encoding to introduce bit sparsity in the most significant bits (MSBs) and an in-memory swapping mechanism for error mitigation. Validated on large-scale datasets with advanced vision transformer (ViT) models, our methods effectively restore the accuracy by 72.08% to 78.56% across various ViT models, eliminating the need for expert-driven retraining.
Event(s)
6th IEEE International Conference on AI Circuits and Systems, AICAS 2024
Publisher
IEEE
Type
conference paper