Design of an Energy-efficient Frequency Digitizer Using 2nd-order Delta-Sigma Modulation Technique
Date Issued
2014
Date
2014
Author(s)
Hsu, Chien-Lun
Abstract
Recently, as the advancement of semiconductor, short range wireless applications like the wireless body area network (WBAN) experience a rapid growth. However, the improvement in battery energy density does not catch up with the semiconductor, traditional transceiver architecture cannot be implemented in low power portable or implantable bio-medical application. Therefore, there exists a critical issue of how to enhance the transceiver energy efficiency. In this work, a 400-MHz GFSK receiver is present. The GFSK signals store the input information in its frequency and are much more robust against channel noise. This work adopted a PLL-based architecture which can track the input frequency to demodulate GFSK signal. The proposed receiver combines RF receiving block with demodulation digitizing block. To get better SNDR, it also adopts the technique of continuous-time delta-sigma modulation. Therefore, it reduces the cost and power consumption by simplifying system architecture. The receiver is fabricated in TSMC 90-nm CMOS technology. It consumes 3.32 mW with 1.2-V supply. The simulated system sensitivity is -76 dBm. The energy efficiency is 1.66 nJ/bit with 2-Mbps input signal.
Subjects
low-power GFSK receiver
GFSK demodulator
frequency digitizer
SDGs
Type
thesis