Design and Implementation of Dual-Band Frequency Synthesizer for IEEE 802.11a/b/g
Date Issued
2005
Date
2005
Author(s)
Lin, Shun-Da
DOI
en-US
Abstract
Recently, the explosively development of the wireless communication system and the rapidly growing market has motivated research and development of the analog transceiver front end. Low-power, low-cost and high-integration integrated circuit has become the trend of the wireless technology. Those characteristic and the progress of the sub-micron CMOS process makes CMOS process has become very attractive process to implement wireless communication systems. Besides, the integration of different system in a single chip has also become the mainstream. At present, IEEE 802.11 series are the main standards of the wireless communication, and 802.11a, 802.11b, and 802.11g are the most extensively used. 802.11a operates around 5 GHz, 802.11b and 802.11g operate at 2.4GHz.
In this thesis, dual-band frequency synthesizer for IEEE 802.11a/b/g has been chosen as the research topic. A dual-band CMOS frequency synthesizer for IEEE 802.11a/b/g, a dual-loop dual-band CMOS frequency synthesizer for IEEE 802.11a/b/g, and an adaptive bandwidth low-power frequency synthesizer are presented. The dual-band function is to generate the doubled-frequency signal by amplifying the second order harmonic of the VCO. The dual-band CMOS frequency synthesizer operates in both 2.4GHz and 5.2GHz while exhibiting a phase noise of -105dBc/Hz@1MHz in 2.4GHz and -84dBc/Hz@1MHz in 5.2GHz. It also exhibits a spur level of -35dBc. It has fabricated in TSMC 0.35-um two-poly, four-metal technology and consumes 39mW. The dual-loop architecture used in the second synthesizer is to enlarge the tuning range with reasonably low noise sensitivity. A 27% frequency tuning range is achieved and exhibits a relatively good phase noise of -112dBc/Hz@1MHz in 2.4GHz and -102.5dBc/Hz@1MHz in 5.2GHz. The spur level is -40dBc. It has also been fabricated in TSMC CMOS 0.35-um two-poly, four-metal technology and consumes 33.7mW from a 3.3V supply. Finally, the adaptive bandwidth enhances the tracking capability by extending loop bandwidth and generates a low phase noise clock signal by lowering the loop bandwidth adaptively. In simulation, it exhibits very low power consumption that the whole synthesizer consumes only 8mW and the programmable divider consumes only 1mW under 1.8V operation. The synthesizer is implemented in 0.18-μm CMOS process and the die size is 0.86mm×0.73mm2.
Subjects
頻率合成器
雙頻
低功率
可適性頻寬
frequency synthesizer
dual-band
low power
adaptive bandwidth
Type
thesis
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