Automatic Multi-Cycle Path Assertion Property Generation in VLSI Designs
Date Issued
2006
Date
2006
Author(s)
Wei, Shih-Kuei
DOI
en-US
Abstract
In this thesis, we proposed an effective method to verify the multi-cycle paths in a gate-level design with the SDC (Synopsis Design Constraint) timing constraints in the design setup file. We analyzed the usage of multi-cycle paths, and summarized it into several types of multi-cycle path structures. Based on the different types of multi-cycle path structures, we generated the assertion properties for them in the format of SystemVerilog assertions. The assertion properties define the behavior of the multi-cycle paths in the design, and they can be used as checkers in the dynamic simulation tool to verify the multi-cycle path timing constraints. In the experiment result, we showed some examples to illustrate the procedure of our approach.
Subjects
積體電路
多時脈路徑
自動化
查驗條件
VLSI
Multi-Cycle Path
Assertion
Property
Type
thesis
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