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College of Electrical Engineering and Computer Science / 電機資訊學院
Electrical Engineering / 電機工程學系
Zero-Aware Asymmetric SRAM Cell for Reducing Cache Power in Writing Zero
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Zero-Aware Asymmetric SRAM Cell for Reducing Cache Power in Writing Zero
Resource
IEEE Transactions on Very Large Scale Integration Systems 12 (8): 827-836
Journal
IEEE Transactions on Very Large Scale Integration Systems
Journal Volume
12
Journal Issue
8
Pages
827-836
Date Issued
2004
Date
2004
Author(s)
Chang, Yen-Jen
Lai, Feipei
FEI-PEI LAI
DOI
10.1109/TVLSI.2004.831471
URI
http://ntur.lib.ntu.edu.tw//handle/246246/142053
http://ntur.lib.ntu.edu.tw/bitstream/246246/142053/1/17.pdf
Type
journal article
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Name
17.pdf
Size
936.26 KB
Format
Adobe PDF
Checksum
(MD5):213500ff32ab38450fb682f991ca1e37
