Efficient VLSI architectures of lifting-based discrete wavelet transform by systematic design method
Resource
Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on
Journal
IEEE International Symposium on Circuits and Systems, ISCAS 2002
Pages
-
Date Issued
2002-05
Date
2002-05
Author(s)
DOI
N/A
Abstract
In this paper, an effective systematic design method is proposed to construct several efficient VLSI architectures of 1-D and 2-D lifting-based discrete wavelet transform. This design method first performs a specific lifting factorization for any finite discrete wavelet transform filter to obtain an optimal algorithm representation for hardware implementation. The optimized algorithm then turns into 1-D systolic architectures through dependence graph formation and systolic arrays mapping. Based on the 1-D architectures, a general 2-D discrete wavelet transform framework is used to construct the corresponding 2-D architectures. According to the comparison results, the constructed VLSI architectures are more efficient than previous arts in term of arithmetic units and memory storage.
Type
journal article
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