Design and Implementation of a Clock and Data Recovery Circuit for 10GBASE-LX4
Date Issued
2005
Date
2005
Author(s)
Hsieh, Yi-Cheng
DOI
en-US
Abstract
The design of Clock and Data Recovery (CDR) circuits is the most complicated part of an optical transceiver. In the near future, 10GBASE-LX4 Ethernet will play an important role in the multi-gigabit optical communication system of Local Area networks (LANs). We use TSMC 0.18μm 1P6M CMOS technology to implement this high speed circuit to achieve low cost, low power consumption, and highly integrated capability.
Since the required Bit Error Ratio (BER) must be less than 10-12, there will be a serious design challenge for the CDR. This Thesis presents a CDR architecture which has dual loop tracking path to achieve better jitter performance. The new phase detector (PD) which reduces the control line ripples makes the VCO oscillating steadily. We also design a two-stage ring VCO with a dual-control node to have low power dissipation, wide tuning range, and better phase noise performance.
The recovery clock exhibits a peak to peak jitter of 2.2ps for a PRBS sequence of length 27-1. The CDR circuit dissipates a total power of 75mW with a 1.8V supply and occupies a die area of 0.75 mm x 0.75 mm.
Subjects
時脈與資料回復電路
CDR
Type
thesis