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College of Electrical Engineering and Computer Science / 電機資訊學院
Electronics Engineering / 電子工程學研究所
Substrate-Bias Optimized 0.18um 2.5 GHz 32-bit adder with Post-Manufacture Tunable Clock
Details
Substrate-Bias Optimized 0.18um 2.5 GHz 32-bit adder with Post-Manufacture Tunable Clock
Journal
VLSI-TSA-DAT
Date Issued
2005-04
Author(s)
Qi-Wei Kuo
Vikas Sharma
CHUNG-PING CHEN
DOI
10.1109/VDAT.2005.1500091
URI
http://scholars.lib.ntu.edu.tw/handle/123456789/318046
Type
conference paper