High Speed 10 Gb/s Digital Logic Programmable Transceiver Testing Platform

Abstract
For developing high speed networking, it is necessary to design a high speed programmable networking testing platform that meets our requirement. Currently, OC-192 transceiver ICs are mature product, but no commercial product to provide chip design platform. Therefore, this thesis presents the developing methods and the implementation results for the design and implement of the high speed programmable networking testing platform.
The FPGA XC2VP70 chip from Xilinx and 16:1 and 16:1 S19237 transceiver chip from AMCC conformed to SONET STS-192 standard are used to design the high speed programmable networking testing platform. With 1704 pins, the FPGA in XC2VP70 has 20 ports that are able to transmit and receive high speed signals up to 3.125 Gb/s. S19237 chip has the function of 16:1 and 1:16 MUX/DeMux for the transmission and receiving of 10 Gb/s signal. The circuit design is complex and challenging with special requirement of the signal integrity. By using the simulation tools, such as ADS (Advance Design System) and control transmission line characteristic impedance software “Polar”, we are able to design 10 Gb/s and 625 Mb/s high speed transmission lines. The high speed signals can be transmitted in the PCB with acceptable signal quality.
In the verification and measurement, the PRBS generator inside FPGA generates sixteen 625 Mb/s signals and these parallel signals are transmitted to the 16:1 MUX, and the MUX outputs a 10 Gb/s PRBS signal. And the eye pattern are measured via DCA ( Digital Communication Analyzer ) to verify the 10 Gb/s transmission ability of this testing platform.