A Sub-Word Parallel Digital Signal Processor for Wireless Communication Systems
Resource
ASIC, 2002. Proceedings. 2002 IEEE Asia-Pacific Conference on
Journal
IEEE Asia-Pacific ASIC Conference
Pages
287-290
Date Issued
2002-08
Author(s)
Y. H. Huang
Abstract
In this paper, we propose a programmable fixed-point digital signal processor for wireless communications. The architecture of the processor is designed according to the computation requirements of modern communication systems. A decimation-in-frequency (DIF) butterfly unit is built in the processor to enhance the processing capability of FFT operations needed in orthogonal-frequency-division-multiplexing (OFDM) systems. In addition, the butterfly unit can be reconfigured to accelerate squared-difference and add-compare-select calculation in the Viterbi algorithms. A new subword parallel complex-valued multiply-and-accumulate (MAC) architecture is proposed to execute complex/real and single/double precision operations, making it suitable for different requirements of signal formats in signal processing for communication transceivers.
Type
conference paper
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