Modern VLSI Routing Considering Reliability and Manufacturability
Date Issued
2009
Date
2009
Author(s)
Chen, Huang-Yu
Abstract
As nanometer technologies of very-large-scale integration (VLSI) advances, design complexity grows at a dramatic speed. Nowadays, a chip may contain several billion transistors and has over one million nets. In the nanometer era, routing has become a decisive factor for determining chip yield, since it presides over most of the layout geometries in the back-end design process. In this dissertation, new routing systems and algorithms are developed to tackle these challenges, for handling (1) increasing chip complexity, (2) reliability, and (3) manufacturability.raditional routing algorithms adopt a two-stage flat framework of global routing followed by detailed routing. However, the flat framework does not scale well as the design size increases. To cope with the scalability problem, a hierarchical framework is proposed, which uses the divide-and-conquer approach to handling smaller subproblems independently. Although the hierarchical approach can scale to larger designs, it has a drawback of lacking interactions among routing subregions and thus limits the solution quality. To remedy the deficiencies, researchers have proposed various multilevel frameworks to handle large-scale routing problems. The λ-shaped multilevel routing framework consists of bottom-up coarsening followed by top-down uncoarsening, while the V-shaped one consists of top-down uncoarsening followed by bottom-up coarsening. The multilevel frameworks demonstrate the superior capability of handling large-scale routing problems and the versatility of tackling modern nanometer electrical effects.ased on these two multilevel frameworks, we develop new routing frameworks, namely TBF (Two-pass, Bottom-up routing Framework) and TTF (Two-pass, Top-down routing Framework), to accelerate the routing speed, enhance the routability, and improve the performance. Moreover, we propose new routing methodologies considering design for reliability and manufacturability issues.o enhance the reliability through redundant-via insertion, we present a new full-chip routing system considering double-via insertion for yield enhancement. To fully consider double vias, the router applies the TBF routability-driven routing framework and features a new redundant-via aware detailed routing algorithm to improve the via count, the number of dead vias, and double-via insertion rates.o increase manufacturability and reduce the post-CMP (chemical-mechanical polishing) topography variation, we present a new full-chip routing system considering wire density for reticle planarization enhancement. To fully consider wire distribution, the router applies the TTF planarity-driven routing framework which employs a density critical area analysis (DCAA) based on Voronoi diagrams and incorporates an intermediate stage of density-driven layer/track assignment based on incremental Delaunay triangulation.o cope with the manufacturing problem considering the layout decomposition in DPT (double-patterning technology), we present a rule-based DPT-aware routing system to reduce conflicts and stitches for grid-based designs. Specifically, our router can guarantee 100% splitting without DPT conflicts, considering vertical-horizontal patterns. The router embeds a fast layout decomposition (FLD) algorithm as a cost evaluator which consists of two major stages: (1) alternating-coloring conflict removal, and (2) two-phase stitch minimization. In addition, the approaches to improve the scalability of the proposed algorithms are also leveraged for large-scale designs.
Subjects
Manufacturability
Physical Design
Reliability
Routing
VLSI
SDGs
Type
thesis
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