Determination of Ultrathin Gate Oxide Thickness (＜2.0 nm) Using Low Dissipation Factor Regions of C－V Measurements
Date Issued
2007
Date
2007
Author(s)
Chang, Po-Kai
DOI
zh-TW
Abstract
With the expeditious development of modern CMOS technology, the equivalent oxide thickness (EOT) of gate dielectric is systematically downscaled into the ultrathin range (＜2.0 nm) and becomes a key factor in the precise determination of many device parameters, such as electron/hole mobility, oxide charge density, interface trap density, breakdown field strength, etc.
However, C－V curves of ultrathin oxides near the accumulation region show a disposition to roll off abruptly due to exponentially-increasing leakage current and series resistance; hence the two-frequency correction method was proposed to work out an empirical solution based on three-element circuit model. Once the oxide thickness shrank down below 2.0 nm, the error of measured capacitance could be dreadfully large, unless the two frequencies were chosen with caution.
In this work, a new approach to the estimation of ultrathin oxide thickness from C－V measurement has been demonstrated. By choosing an adequate interval on the C－V curve where the dissipation factor is low enough, we can perform a simple linear regression, then comparing the experimental slope with theoretical values to find out the actual oxide thickness. This technique is valid for a 1.6 nm SiO2 capacitor, while the two-frequency correction method can hardly determine the correct value.
Subjects
超薄氧化層
等效厚度判定
散逸因子
Ultrathin Oxide
EOT determination
Dissipation Factor
Type
thesis
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