A 62.5-625MHz anti-reset all-digital delay-locked loop
Journal
IEEE Transactions on Circuits and Systems II: Express Briefs
Journal Volume
54
Journal Issue
7
Pages
566-570
Date Issued
2007-07
Author(s)
Abstract
An anti-reset all-digital delay-locked loop (DLL) is presented. When the input clock frequency changes significantly, the dynamic frequency detector re-locks the DLL without any external reset signal. The proposed binary time-to-digital converter (BTDC) reduces effectively the hardware, compared with a conventional TDC. Unlike many previous all-digital DLLs, this one is a closed feedback loop that can track environmental variations. The input frequency range can be operated from 62.5-625 MHz. It spends at most six cycles to synchronize the input and output clocks. © 2007, IEEE. All Rights Reserved.
SDGs
Other Subjects
Closed loop control systems; Detector circuits; Feedback control; Synchronization; Delay-locked loop; Dynamic frequency detector; Frequency range; Time-to-digital converter; Delay circuits
Type
journal article