H.264畫面內編碼電路之設計與製作
Design and Implementation of an H.264 Intra-frame Coding Circuit
Date Issued
2005
Date
2005
Author(s)
Chu, Cheng-Wei
DOI
en-US
Abstract
In this Thesis, we propose a design of H.264 intra frame coding circuit. In the proposed design, nine INTRA_4x4 and four INTRA_16x16 prediction modes for luminance samples are realized, and four INTRA_CHROMA prediction modes for chrominance samples are also implemented. The design owns a processing capability to accomplish the H.264 intra frame coding for SDTV (720 x 480 x 30 fps) application.
The architecture of intra prediction generator is designed to support all prediction modes defined in the H.264 standard. Forward/inverse transform unit proposed in [5] is adopted. Architectures of Quantization, Dequantization and Mode Decision units have also been designed. Every stage in our design can process four pixels per clock. A microblock (MB) with full prediction case will spend 1350 clocks to accomplish all prediction modes.
A prototype of the proposed design was implemented in UMC 0.18um 1P6M process technology and fabricated by CIC. The maximum operation frequency of our design in post-layout simulation is 55.56 MHz. This processing capability is sufficient for the requirement in SDTV (720 x 480 x 30 fps) intra frame encoding. The die size is 2.374 x 2.434 mm2, and gate count is about 201k.
Subjects
H.264
畫面內編碼器
Intra-frame Coding
Type
thesis
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