Single chip video segmentation system with a programmable PE array
Resource
ASIC, 2002. Proceedings. 2002 IEEE Asia-Pacific Conference on
Journal
2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings
Pages
233-236
Date Issued
2002
Author(s)
Abstract
Video segmentation is a very important unit in content-based video encoding systems, such as MPEG-4. In this paper, a single chip video segmentation system is proposed. First, a hardware-oriented video segmentation algorithm is developed, which contains only local pixel operations and morphological operations. Simulation results show that the segmentation results of the proposed algorithm are satisfied. To achieve both high throughput and flexibility, the system is then mapped to a hardware architecture with a programmable PE array. This chip is designed with cell-based design flow and is currently under fabrication by TSMC using 0.35μm 1P4M technology. Simulation shows that the prototyping chip can achieve the processing speed of 30 QCIF frames per second and 7,680 binary morphological operations per second at 26MHz with small chip size. This chip can be integrated into any camera or real-time encoding system to support content-based coding capability. © 2002 IEEE.
Event(s)
3rd IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002
Other Subjects
Encoding (symbols); Hardware; Mathematical morphology; Motion Picture Experts Group standards; Reconfigurable hardware; Content based coding; Content based video encoding; Hardware architecture; Morphological operations; Real-time encoding; Segmentation results; Video segmentation; Video segmentation algorithms; Image segmentation
Type
conference paper
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