Design of a Continuous-Time Delta Sigma Modulator with Circular TDC-based Quantizer and Inherent DEM

A third-order multi-bit continuous-time delta-sigma modulator is presented in this thesis. Because the non-linearity of digital-to-analog circuit (DAC) degrades the performance of the signal to noise distortion ratio, conventional modulators adopt dynamic element matching technique to alleviate the problem. However, it consumes extra loop delay for dynamic element matching circuit, so the conversion time of the quantizer is squeezed. On the other hand, digital converters (time-to-digital converter) outperform analog converters in advanced processes. Therefore, in this thesis, inherently dynamic element matching time-to-digital converter-based quantizer is proposed. In addition, this work proposes a new technique to reduce the quantizer level by two-step quantizer, leading to area and power reduction.
This continuous-time delta-sigma modulator is implemented in a TSMC 90-nm CMOS process. The proposed modulator achieves a 69.6-dB peak SNDR with a 1-MHz bandwidth at a 64-MHz sampling rate and has an 72-dB dynamic range. The implemented modulator dissipates only 1.8 mW from a analog 1.2-V and digital 1-V supply. FoM is 360 fJ/conv.