A 0.6 V 1.63 fJ/c.-s. Detective Open-Loop Dynamic System Buffer for SAR ADC in Zero-Capacitor TDDI System
Journal
IEEE Journal of Solid-State Circuits
Journal Volume
54
Journal Issue
10
Pages
2680-2690
Date Issued
2019
Author(s)
Abstract
In this paper, a low-power detective open-loop dynamic (DeOLD) system buffer codesigned with a SAR ADC that is pertinent for zero-capacitor touch with a display driver integration (TDDI) system is proposed. The proposed DeOLD system buffer not only blocks the supply coupling interference off the ADC but also compensates the lost charge back to the supply by actively detecting the ADC input signal. Its third-harmonic distortion is suppressed to under 70 dB. The dynamic charge sharing technique reduces the power of the charge compensators by 40% compared with the well-known pump squeezing technique. A supply reset (RST) circuit makes up the charge loss and avoids the usage of an unpractical charge compensator to save additional chip area and energy. The system buffer is open loop, which is fast and energy-efficient; furthermore, it is codesigned with a 400-kS/s 10-b SAR ADC. The system buffer provides all voltage sources for the ADC, including the reference, digital, and analog voltages. It consumes 334 nW under a 0.6-V supply. Its active area is only 0.0098 mm2 in 40-nm CMOS technology. It achieves an signal-to-noise and distortion ratio (SNDR) of 55.96 dB, resulting in the Walden figure-of-merit (FoMW) of 1.63 fJ/c.-s.
SDGs
Other Subjects
Energy efficiency; Signal to noise ratio; Charge compensators; Dynamic charges; Open loop dynamics; Open loop operation; SAR ADC; Signal to noise and distortion ratio; system buffer; Third harmonic distortions; Analog to digital conversion