A divider-less sub-harmonically injection-locked PLL with self-adjusted injection timing
Journal
Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Journal Volume
56
Pages
414-415
Date Issued
2013
Author(s)
Abstract
A low-phase-noise phase-locked loop (PLL) is widely used in clock generation, frequency synthesis, and data conversion. In [1,2], a PLL using a sub-sampling phase detector (SSPD) achieves not only low phase noise, but also low power. In [3-5], a low-phase-noise sub-harmonically injection-locked PLL (SIPLL) is presented. The injection timing of a SIPLL is sensitive to the process, voltage, and temperature (PVT) variations [1-3,5]. In addition, the divider of a SIPLL [3-5] cannot be powered down to save the power as in [1,2]. In this paper, a divider-less SIPLL with self-adjusted injection timing is presented. © 2013 IEEE.
SDGs
Type
conference paper