Design and Implementation of a Timing-Error Detection and Correction Mechanism on ARM1136
Date Issued
2015
Date
2015
Author(s)
Luo, Cheng-Hao
Abstract
With the growing popularity of mobile devices, the trend in the field of system-on-chip has shifted from high performance to low power operation. However, traditional design methodology is limited by the design margins reserved for process, voltage and temperature variations. The operating point is chosen under a worst-case scenario of variations for the circuit to operate correctly. This design methodology is the so called worst-case design. On the other hand, it is possible to reduce the design margins if timing error is detectable and recoverable, which leads to prominent energy saving and better reliability compared with the worst-case design. In this Thesis, a systematic solution that enables real-time timing error detection and correction was proposed to eliminate redundant design margins and implement it on an ARM microprocessor. We build a hybrid error detection mechanism that combines global and local timing information to detect errors. The error correction mechanism is implemented on architectural-level based on instruction replay, and a frequency control mechanism is added to prevent possible deadlock situation caused by repeated errors. To better utilize the underlying error-tolerance mechanism, an activity-driven optimization procedure is proposed to reshape the slack distribution based on path activity. As a result, the design becomes more robust against process, voltage, and temperature variations. On the other hand, the power efficiency increases due to the reduction of design margins, thus making it a better-than-worst-case design.
Subjects
Design Margins Elimination
Error Detection
Error Correction
Type
thesis
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