A CMOS ΔΣ fractional-N frequency synthesizer with quantization noise pushing technique
Journal
IEEE Symposium on VLSI Circuits, Digest of Technical Papers
Pages
262-263
Date Issued
2007
Author(s)
Abstract
A ΔΣ fractional-N frequency synthesizer with a quantization noise pushing technique is implemented in a 0.18um CMOS technology. The in-band phase noise can be lowered by 12 dB, and the out-band phase noise contributed by the ΔΣ modulator can be reduced by more than 15dB with this technique. The power consumption is 26.8mW from a 2V supply.
SDGs
Type
conference paper