Gate Direct Tunneling Leakage Behavior Analysis of 60nm PD SOI NMOS Device

The thesis reports the analysis and the modeling of the gate tunneling leakage current behavior of 60nm PD SOI NMOS device using shallow trench isolation(STI). First the evolution of the SOI device and its characteristics with the trend of gate oxide thickness and the related gate current are introduced in Chapter 1. In Chapter 2, the floating-body-effect-related gate tunneling leakage current behavior of 60nm PD SOI NMOS device is presented. The turn-on of parasitic bipolar of the device not only causes kink effect but also affects the gate tunneling leakage current as verified by the experimental data and simulation results. The vertical electric field in lateral channel direction and the current density distribution of the U-shaped edges of the poly-silicon gate determine the gate tunneling leakage current. In Chapter 3, via using SPICE the partitioned charge model of the SPICE gate tunneling urrent model has been used in characterizing IG. Based on the SPICE model with the finely-tuned parameters, the gate leakage current of the 60nm PD SOI NMOS device could be accurately predicted. Chapter 4 is the conclusion and the future work.